1. Field of the Invention
The present invention relates to the technical field of semiconductor wafer production, particularly to a silicon wafer wherein the occurrence of both slip dislocations and warpages during a device production process can be suppressed, and to a process for producing the same.
2. Description of the Related Art
A silicon wafer used as a substrate for semiconductor devices is produced by slicing a silicon single crystal ingot and subjecting the sliced wafers to heat treatment, mirror finishing, and the like. One process for producing silicon single crystal ingots is the Czochralski method (CZ method). The CZ method accounts for a major part of processes for producing silicon single crystal ingots since it makes it possible to easily obtain a single crystal ingot with a large diameter and to control defects relatively easily.
A silicon single crystal pulled by the CZ method (hereinafter, “CZ-Si”) includes crystal defects called “grown-in defects”. The CZ-Si contains oxygen between lattice points in a supersaturated state, and such supersaturated oxygen causes the induction of fine defects called Bulk Micro Defects (hereinafter, “BMD”) in subsequent heat treatments (anneals).
The formation of a semiconductor device on a silicon wafer requires no crystal defects in the semiconductor device formation region. If crystal defects are present on a surface where a circuit is formed, a circuit breakage is caused by the defects. Meanwhile, a silicon wafer is required to include a proper amount of BMDs inside, since BMDs serve to getter metal impurities, which cause semiconductor device malfunction.
To fulfill the above requirements, a process is used whereby an Intrinsic Gettering layer (hereinafter, “IG layer”) is formed by inducing BMDs inside a silicon wafer by annealing the silicon wafer at a high temperature, while eliminating grown-in defects present on the surface of the silicon wafer to form a Denuded Zone (hereinafter, “DZ layer”) having hardly any crystal defects.
As a concrete example, JP 10-98047 discloses a process whereby grown-in defects on a surface are reduced by annealing a nitrogen doped substrate at a high temperature, while BMDs containing nitrogen as nuclei are formed inside the substrate. However, oxygen concentrations in DZ layers formed on the front and back faces of the silicon wafer by the above-mentioned high-temperature annealing process are extremely low because of the external diffusion of oxygen during heat treatment. As a result, restraint of dislocation propagation on the front and back faces of a wafer is considerably reduced, and dislocation defects (hereinafter, “slips”) easily extend from fine flaws introduced during the annealing process into the bulk from the front and back faces of the wafer. As a result, the strength of the silicon wafer is reduced because of the slip dislocation extension. For example, when a silicon wafer is annealed in a state supported by heat treatment supports, slip dislocations often extend from the supported portions around the back face of the wafer. In addition, slip dislocations sometimes extend from the edge of a silicon wafer.
When the strength of a silicon wafer is reduced, the wafer could be damaged or broken during a production process. However, DZ layers are inevitable for semiconductor device formation, and thus a silicon wafer having DZ layers while also excelling in strength properties has been desired.
In the process of JP 10-98047 previously discussed, reduction of silicon wafer strength was not considered, and in a silicon wafer produced thereby slip dislocation propagation cannot be avoided.
Meanwhile, in order to prevent the occurrence of such slip dislocations, a process whereby BMDs are generated in a high density has been proposed. Specifically, JP 2006-40980 discloses a silicon wafer production process wherein a substrate cut out of a silicon single crystal ingot is subjected to a rapid temperature increasing/decreasing heat treatment in an atmosphere of nitrogen gas, inert gas, or a gas mixture of ammonia and inert gas, at a temperature of 500° C. to 1,200° C. for 1 to 600 minutes, to form oxygen precipitation nuclei with sizes of 20 nm or less in a density of 1×1010 defects/cm3 or more in a BMD layer. A silicon wafer wherein BMDs are generated in a high concentration (1×1010/cm3 to 1×1012/cm3) by repeating heat treatment steps several times, has also been proposed by JP 08-213403.
In recent years, because the diameter of silicon wafers has been increased and the degree of integration of semiconductor devices has also been increased, warpage of wafers has become problematic in addition to the problem of slip dislocations.
A typical example of slips and warpages introduced by heat treatment is shown in FIG. 1. Heat treatment furnaces roughly include two kinds of furnaces, a batch furnace and an RTA (Rapid Thermal Annealer). Since the degree of heat distortion is different between both furnaces, the manner of warpage and slip occurrence in a wafer is also different. Slips are introduced from a contacting point between a wafer back face and a wafer holding portion, or from a wafer edge part. The introduced slips extend in a {110} direction, and sometimes cause wafer damage or breakage. Warpage is a deformation caused by heat distortion during a heat treatment. On a wafer of {100} plane, for example, hill- and valley-shaped parts appear, as shown in FIG. 1. Warpage of silicon wafers prior to subsequent heat treatment for altering wafer properties is usually suppressed to not more than 10 μm. After a heat treatment like RTA, however, the difference in the height between the hill- and the valley-shaped parts sometimes increases up to tens of μm. A large warpage prevents accurate exposure of a semiconductor device pattern on a wafer surface, causing the reduction in the yield of semiconductor devices.
The problem of warpages becomes serious when the wafer diameter is 200 mm or more. This problem could not be avoided simply by requiring a high density of BMDs as above.